| ??? 09/29/05 13:00 Read: times |
#101714 - Only need one latch Responding to: ???'s previous message |
The latch is for the lower half of the address. Addresses are not bi-directional, they're outbound from the uC only. ALE triggers the latch to hold the LSB, which gets presented on P0. The MSB gets presented on P2. After the address is presented, RD or WR is presented, and the data is read or written from P0. The latch is simply there to hold the LSB so that P0 can be reused to read/write the data. PSEN only comes into play if you have external program memory.
The only reason I could see you needing a '244 or '245 would be if you exceeded the fanout on these ports. Unless you're running a 8032 with BASIC in an external ROM, a basic system only needs the latch, and the RAM, which should be within the ability of the uC to drive. Rob |
| Topic | Author | Date |
| Buffering address/data bus Basic-52 | 01/01/70 00:00 | |
| direction | 01/01/70 00:00 | |
| Yes | 01/01/70 00:00 | |
| '573? | 01/01/70 00:00 | |
| 245 | 01/01/70 00:00 | |
| Only need one latch | 01/01/70 00:00 | |
| Re-read this... | 01/01/70 00:00 | |
| negative logic | 01/01/70 00:00 | |
| caqll a spade a spade | 01/01/70 00:00 | |
| Ok... I follow you, but... | 01/01/70 00:00 | |
| 74F623 instead of 74F245 | 01/01/70 00:00 | |
| I'd stick with a 245 | 01/01/70 00:00 | |
74AC623 is also fast | 01/01/70 00:00 | |
| A little clarification | 01/01/70 00:00 | |
| if you are ANDing them it will never wor | 01/01/70 00:00 | |
| How fast is your memory? | 01/01/70 00:00 |