| ??? 09/29/05 14:54 Read: times |
#101727 - negative logic Responding to: ???'s previous message |
Rob Vassar said:
Providing I'm reading this right... What happens when the uC tries to read from RAM? PSEN will not be asserted, and the RD signal will not get to the '245. Probably not enough coffee. Both /PSEN and /RD are active LOW (and so are the control signals (/CS, /OE, /WE) of almost all memories). AND is in fact OR for negative logic. Rob Vassar said:
PSEN only determines which bank of memory you're accessing. RD/WR determine which direction the buffer should run. Add more coffee. This is how some processors behave, but not the '51. /PSEN is active when code is fetched from external memory (or MOVC is used); /RD is active when data is read from external memory using MOVX (/WR is active when data is written to external memory using MOVX). To have some part of memory accessible both as code memory and as MOVX-accessible memory, the /PSEN and /RD have to be "combined" - see above. The address latch ('573) should not interfere with the data buffer ('245) (unless the latter is placed between the '51 and the '573, which would be pure nonsense) Jan Waclawek |
| Topic | Author | Date |
| Buffering address/data bus Basic-52 | 01/01/70 00:00 | |
| direction | 01/01/70 00:00 | |
| Yes | 01/01/70 00:00 | |
| '573? | 01/01/70 00:00 | |
| 245 | 01/01/70 00:00 | |
| Only need one latch | 01/01/70 00:00 | |
| Re-read this... | 01/01/70 00:00 | |
| negative logic | 01/01/70 00:00 | |
| caqll a spade a spade | 01/01/70 00:00 | |
| Ok... I follow you, but... | 01/01/70 00:00 | |
| 74F623 instead of 74F245 | 01/01/70 00:00 | |
| I'd stick with a 245 | 01/01/70 00:00 | |
74AC623 is also fast | 01/01/70 00:00 | |
| A little clarification | 01/01/70 00:00 | |
| if you are ANDing them it will never wor | 01/01/70 00:00 | |
| How fast is your memory? | 01/01/70 00:00 |