Buffering the data bus of a 89C52 is difficult, if you want to provide enough data hold times and surely avoid bus contention.
If I had to buffer the data bus, then I would try the following scheme:





The circuit works as follows:
The upper 74F623 buffers the data bus, while the lower one buffers the read and write command lines.
The upper buffer is high ohmic on both sides most of the time. Only when a write or read command takes place, one and only one of both sides becomes low ohmic (direction B to A or direction A to B). The lower buffer is turned-on all the time (direction B to A).

When data is to be written to the data memory, data is only threspassed by the upper buffer, when /WR goes low. If /WR goes high again, data is written into the data memory. In order to provide enough data hold time, turning-off the buffer is a bit delayed. This is done by taking the buffered /WR signal and by inserting two inverters. If minimum data hold time of data memory (or whatever is connected there) is zero, then the both inverters can be neglected.

When data is read by the micro, then the according data is only threspassed by the upper buffer, when either /PSEN or /RD goes low. As the standard 89C52 does not need any data hold time when reading the data bus, no additonal delay is needed, allthough the NAND gate does provide some.

In very fast systems, data hold times must not be too long. Here a careful analysis of timing regarding to tPXIZ and tRHDZ is neccessary. The use of 74F00 and 74F623 might be urgently needed then. On the other hand, if clock frequency of micro is rather low, then 74F-TTL logic isn't needed and some slowlier chips can be used instead.

Kai