| ??? 12/19/05 18:04 Read: times |
#105541 - Open drain suffers from big rise time Responding to: ???'s previous message |
Vignesh said:
Hi, I would like to interface 89S8252(12MHz, 5V) with a FPGA(3.3V). Can I use the following for Sclk, MOSI, and MISO? What FPGA? Can you give us a link to datasheet? Vignesh said:
The gate is 74HC09(sorry it is LS in the schematic)open collector AND, pull up is 1kOhm. These open drain circuits show a drastical disadvantage: When the output transistor turns-off, no active output stage is there, which could drive the output high. Instead of this, stray capacitance is charged-up by the pull-up. If this stray capacitance now is rather high, then rise time of signal, which is about 2.3 x 1k x "stray capacitance" can be higher than maximum input rise time of FPGA. In this case input of FPGA can oscillate, which would totally erode signal integrity at this point. So, either input rise time requirements of FPGA are fullfilled by your circuit or there's a Schmitt trigger needed at input of FPGA, maybe an already built-in one. Or, you follow Erik's recommedation, which would totally eliminate such interface problems. Kai |
| Topic | Author | Date |
| 5 - 3.3V conversion | 01/01/70 00:00 | |
| 74lvc4245 available from Philips, TI and | 01/01/70 00:00 | |
| Package and MOQ? | 01/01/70 00:00 | |
| Where is the problem? | 01/01/70 00:00 | |
| English! | 01/01/70 00:00 | |
| I did not suggest an AND gate | 01/01/70 00:00 | |
| I am a novice.. | 01/01/70 00:00 | |
| many components introduced the last 3-5 | 01/01/70 00:00 | |
I would learn | 01/01/70 00:00 | |
| Open drain suffers from big rise time | 01/01/70 00:00 | |
| FPGA | 01/01/70 00:00 | |
| Origin of oscillation | 01/01/70 00:00 | |
| Deep Inside! | 01/01/70 00:00 | |
| If connections are short... | 01/01/70 00:00 | |
| Thankyou | 01/01/70 00:00 |