| ??? 12/19/05 18:45 Modified: 12/19/05 18:47 Read: times |
#105546 - Origin of oscillation Responding to: ???'s previous message |
Vignesh said:
Sorry dear Kai, how will it oscillate? The region of input/output curve where the output toggles is a very critical point of high instability. Each chip family specifies a minimum transition time that is needed to traverse this critical point of input curve. For 74HCMOS for instance, minimum input rise and fall time of input signal is 500nsec (@ Vcc = 5V). If the signal changes slowlier, then a portion of output voltage can feedback to input via on-chip stray capacitance and make it oscillate. Beside the erodation of signal integrity, this oscillation can destroy the input gate, which oscillates! Kai |
| Topic | Author | Date |
| 5 - 3.3V conversion | 01/01/70 00:00 | |
| 74lvc4245 available from Philips, TI and | 01/01/70 00:00 | |
| Package and MOQ? | 01/01/70 00:00 | |
| Where is the problem? | 01/01/70 00:00 | |
| English! | 01/01/70 00:00 | |
| I did not suggest an AND gate | 01/01/70 00:00 | |
| I am a novice.. | 01/01/70 00:00 | |
| many components introduced the last 3-5 | 01/01/70 00:00 | |
I would learn | 01/01/70 00:00 | |
| Open drain suffers from big rise time | 01/01/70 00:00 | |
| FPGA | 01/01/70 00:00 | |
| Origin of oscillation | 01/01/70 00:00 | |
| Deep Inside! | 01/01/70 00:00 | |
| If connections are short... | 01/01/70 00:00 | |
| Thankyou | 01/01/70 00:00 |