| ??? 12/19/05 18:35 Read: times |
#105545 - FPGA Responding to: ???'s previous message |
Dear Kai, the FPGA is Spartan 2 from Xilinx and it is already in a board which has Chipcon CC2420 radio. The FPGA functions as glue logic, and the datasheet of the Chipcon board advices not to use 5V signals since the FPGA pins are not 5V tolerant.
Kai said:
If this stray capacitance now is rather high, then rise time of signal, which is about 2.3 x 1k x "stray capacitance" can be higher than maximum input rise time of FPGA. Ya, understood, then: In this case input of FPGA can oscillate, which would totally erode signal integrity at this point. Sorry dear Kai, how will it oscillate? Cheers, Vignesh |
| Topic | Author | Date |
| 5 - 3.3V conversion | 01/01/70 00:00 | |
| 74lvc4245 available from Philips, TI and | 01/01/70 00:00 | |
| Package and MOQ? | 01/01/70 00:00 | |
| Where is the problem? | 01/01/70 00:00 | |
| English! | 01/01/70 00:00 | |
| I did not suggest an AND gate | 01/01/70 00:00 | |
| I am a novice.. | 01/01/70 00:00 | |
| many components introduced the last 3-5 | 01/01/70 00:00 | |
I would learn | 01/01/70 00:00 | |
| Open drain suffers from big rise time | 01/01/70 00:00 | |
| FPGA | 01/01/70 00:00 | |
| Origin of oscillation | 01/01/70 00:00 | |
| Deep Inside! | 01/01/70 00:00 | |
| If connections are short... | 01/01/70 00:00 | |
| Thankyou | 01/01/70 00:00 |