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???
08/11/06 14:04
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 		 #122049 - FPGA option
Responding to: ???'s previous message
I think FPGA will come to the rescue, once I get the data I will consider both options.
If the fpga receives the bits and converts them into parallel data, that for sure will speed things up.
Mahmood

List of 36 messages in thread
TopicAuthorDate
5 bit CRC polynomial            01/01/70 00:00      
   there are several            01/01/70 00:00      
   what does "no success" mean?            01/01/70 00:00      
      He said            01/01/70 00:00      
         maybe we need a new 'forum' where            01/01/70 00:00      
      They said            01/01/70 00:00      
         This must be a very smart shaft encoder            01/01/70 00:00      
            competitor like Kuebler            01/01/70 00:00      
         This must be a very smart shaft encoder            01/01/70 00:00      
         Brute force it.            01/01/70 00:00      
            Yes this is what we were doing            01/01/70 00:00      
   can you find it in the pascal here? -- Kai            01/01/70 00:00      
      zyklische Redundanzprüfung            01/01/70 00:00      
      I searched all their site            01/01/70 00:00      
         did you search the pascal code examples            01/01/70 00:00      
            Where?            01/01/70 00:00      
               I did not look at it all, but there is much here            01/01/70 00:00      
                  I downloaded them all            01/01/70 00:00      
                     what about all the .pas            01/01/70 00:00      
      Found a document name            01/01/70 00:00      
         I feel your pain            01/01/70 00:00      
            This is how we get experienced            01/01/70 00:00      
               CRC time            01/01/70 00:00      
                  FPGA option            01/01/70 00:00      
                  SiLabs            01/01/70 00:00      
               have you seen this?            01/01/70 00:00      
                  Maybe it is X^5+X^4+X^3+X^2+X+1            01/01/70 00:00      
   rather than all that processing            01/01/70 00:00      
      The thing is            01/01/70 00:00      
         USB 5bit CRC            01/01/70 00:00      
         implementing other crc using crc package            01/01/70 00:00      
            impressive            01/01/70 00:00      
   rather than all that processing            01/01/70 00:00      
   Initial value?            01/01/70 00:00      
      and the final value            01/01/70 00:00      
   Friends            01/01/70 00:00      

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