This code fits in a $2.00 cpld and checks the crc on the serial bit stream,it uses the crc package generated here http://www.easics.com/webtools/crctool

<pre>
library IEEE;
use IEEE.std_logic_1164.all;
use work.crc5.all;

entity crccheck is
port (reset :in std_logic;
din :in std_logic; --serial data in
clk :in std_logic;
sr :out std_logic; -- goes high every 18 data bits
crc_err :out std_logic)
; -- after 18 data bits have been clocked in the internal shift register holds the MSB
--in bit position 18,sr goes high from the end of one 18 bit data set to the start of the
-- next
end crccheck;

architecture rtl of crccheck is

signal crcreg :std_logic_vector(17 downto 0);


begin
process(clk,reset)
variable bitcount :integer range 0 to 18;
begin
sr<='0';
if reset='0' then
bitcount:=0;
crcreg <=(others=>'0');
crc_err<='0';

elsif rising_edge(clk) then
bitcount:=bitcount+1;
crcreg<=din & crcreg(17 downto 1);
if bitcount=18 then
bitcount:=0;
sr<='1';
if nextCRC5_D13(crcreg(17 downto 5),crcreg(4 downto 0))/=crcreg(4 downto 0) then
crc_err<='1';
else crc_err<='0';
end if;
end if;
end if;

end process;


end rtl;