If you click on the link http://www.easics.com/webtools/crctool
you can define your custon polynomial by just clicking the appropriate boxes and then apply,set the data bus width and then generate which is how is how I produced and downloaded the package used in the code i posted.It produces a vhdl package which you compile and use with a use work.your_package.all and then you call the function defined in the package like so :-
if nextCRC5_D13(crcreg(17 downto 5),crcreg(4 downto 0))/=crcreg(4 downto 0)
I just set the polynomial and data width and it produced this package

library IEEE;
use IEEE.std_logic_1164.all;

package PCK_CRC5_D13 is

-- polynomial: (0 1 2 3 4 5)
-- data width: 13
-- convention: the first serial data bit is D(12)
function nextCRC5_D13
( Data: std_logic_vector(12 downto 0);
CRC: std_logic_vector(4 downto 0) )
return std_logic_vector;

end PCK_CRC5_D13;

library IEEE;
use IEEE.std_logic_1164.all;

package body PCK_CRC5_D13 is

-- polynomial: (0 1 2 3 4 5)
-- data width: 13
-- convention: the first serial data bit is D(12)
function nextCRC5_D13
( Data: std_logic_vector(12 downto 0);
CRC: std_logic_vector(4 downto 0) )
return std_logic_vector is

variable D: std_logic_vector(12 downto 0);
variable C: std_logic_vector(4 downto 0);
variable NewCRC: std_logic_vector(4 downto 0);

begin

D := Data;
C := CRC;

NewCRC(0) := D(12) xor D(7) xor D(6) xor D(1) xor D(0) xor C(4);
NewCRC(1) := D(12) xor D(8) xor D(6) xor D(2) xor D(0) xor C(0) xor
C(4);
NewCRC(2) := D(12) xor D(9) xor D(6) xor D(3) xor D(0) xor C(1) xor
C(4);
NewCRC(3) := D(12) xor D(10) xor D(6) xor D(4) xor D(0) xor C(2) xor
C(4);
NewCRC(4) := D(12) xor D(11) xor D(6) xor D(5) xor D(0) xor C(3) xor
C(4);

return NewCRC;

end nextCRC5_D13;

end PCK_CRC5_D13;