The I2C protocol has a provision for the slave device to get onto the SCL line and hold it low as a means of asserting an asynchronous wait into an ongoing transaction from the master. So in that regard it can be a bit more useful than SPI. The achievable clock rates on the other hand are another thing.

Some additional considerations to think about:

Many sample code drivers on the web and in code libraries that implement bit banged master mode I2C protocol neglect to properly take into account that the slave may be holding the clock low.

With the hardware I2C peripherals that I have used to implement slave devices the hardware interface takes in an byte from the master and then automatically grabs onto the clock line and pulls it low until the slave MCU gets the I2C device interrupt and responds to it. This greatly simplifies the design of slave mode device firmware. However if the slave is slow to respond because it has interrupts disabled or masked for long periods of time then this can seriously extend the net transaction time on the bus and limit throughput, expecially in a multi-slave bus connection.

- mkaras