Hi,
just for interest:

some devices like Atmel`s RD2, RE2 etc have "multiple master collision" feature implemented into their SPI engine.
How it works: if master detects low level on its /SS pin then:

- an SPI receiver/error CPU interrupt request is generated;
- the SPEN bit is cleared (this disables SPI);
- MSTR bit is cleared also.

Indeed, this is not elegant way to insert wait states by dropping master into violation routine.

Regards,
Oleg