I am looking at some old, inherited, Winbond stuff using the Winbond 516B. We found a flakiness and went far back in the releases and saw that it was there, just extremely rare. The frequency increased when some speedup was implemented.

i am suspicious of the auxram use. The crummy Winbond datasheet does not give any details, just a crummy example and do not even bother explaining the CHPENR SFR.

anyhow

the 'example' of writing to the auxram in the datasheet (of course, they had to photograph it so I have to retype) is
mov CHPENR,#87h
mov CHPENR,#59h
mov CHPCON,#010h
mov CHPENR,#0
mov r0,#012h
mov a,#34h
mov @r0,a

now in the actual inherited code it is done as follows

in the 'general' initialization routine:
mov CHPENR,#87h
mov CHPENR,#59h

to write to the auxram
orl CHPCON,#010h
mov r0,#012h
mov a,#34h
mov @r0,a
anl CHPCON,#0efh

I have surmised (I hate having to do that) that the CHPENR simply is 'allow write to auxram'.

now for the question
will the indicated use of the SFRs give any problems (I do not care about write protect).

What I am hunting is an occasional overwrite of the most crummy shared resources scheme between two processors I have ever seen. Example ALE is not connected and they share 32k of RAM, all I/O is MMIO and goes through the same crummy allocation hardware.

in advance, thanx

Erik

PS to show how flaky this is, if I use Philips chips with the same code (the only change is a hardware deteremind different auxram access method) the thingy works. However with an istalled base in the ten thousands, I can not start wholesale replacing chips.