Namely that there's a shortage of I/O's, and no shortage of internal resources where the CPLD is concerned. The notion of the adder comes from the fact that what happens whenever there's a data memory read to 0xC000 and above, is that the logic adds a four to the top nybble of the 18-bit address, limiting the range to what will fit in the available 256 kB of SRAM.

At this moment, I'm considering using a completely different circuit, perhaps with a larger pin-count CPLD, whereby I can put all the latches, etc, in the CPLD and operate on each memory IC separately. That might prove much more flexible. Those old 5-volt 128-macrocell CPLD's cost about $3 last time I bought them, while the 72 macrocell PLCC-44 types cost twice that. They're both 7 ns parts ...

RE