Well, Richard, it appears that you are going to do something really weird - and you will need to cope with that yourself, then.

However, a few concluding remarks.

If you intend to capture a long stream of data, do some processing and transmission to PC, you might consider double- or multiple-buffering schemes. Those fast (cache) SRAMs are not that expensive, especially if you pull them from thrown-out old PC motherboards.

I would drop the PLL-ish thing, too, for simplicity, and post-process the raw stream - whatever it is - in PC, but we discussed that earlier.

Also, you don't really need to address the "sampling" memory from the '51, as you are most probably going to use the sampled data exclusively sequentially. I used this trick once - the addresses are fed from a counter (in the CPLD) advancing at each read cycle, the only thing you need is a facility to reset the counter from '51. This would require a separate chip for the intermediate data and code, though.



A link just for inspiration, both for the idea and for "homemade realisation": http://www.myplace.nu/avr/dram/index.htm

Jan