| ??? 10/21/07 02:16 Modified: 10/21/07 02:27 Read: times |
#145964 - Do you understand why that was done? Responding to: ???'s previous message |
Mike Stegmaier said:
I have looked at this URL:
http://pjrc.com/tech/8051/board5/schematic.html and I noticed that there could be a data fight. Why? Because the designer seemed to connect an address pin of the 8052 to the R/W pin of the HD47780 compatible LCD, and (s)he decided to tie RD, WR, and PSEN of the 8052 together through AND gates to produce one output and connected that output to the LCD enable through a NOR gate. The other end of the NOR gate is connected to an address decoder. My issue is that if the address pin that controls R/W is set to Read, and the enable is active, and the micro wants to write data, then I can see adata clash going on since the micro AND the LCD are outputting data at the same time, and on the same data lines. I think that the way (s)he designed the circuit is done in a bad way. What do you guys think about the circuit? EDIT: I just looked at the 8052 SBC posted at this site after posting the above message, and it seems that its RW pin on the LCD is directly connected to an address line of the micro. There are many ways in which to skin a cat. It's valid to use address lines to provide certain functions, so long as you know what that does. It's also valid to "von-Neumanize" an 805x circuit, which is what's been done in the PJRC circuit you cite. That means that data and code space are unified by virtue of the negative-logic OR of nPSEN and nRD via gate 4 of the 'AC08. That gate will produce a low output whenever a READ or PROGRAM FETCH cycle is performed. Note that the FLASH and the SRAM are both output-enabled by this signal. Further, when that signal, on pin 11 of the 'AC08, is low, the output on pin 8 is low also, as gate 3 of the same IC is also used as a negative logic OR with nWR providing the other input. Hence, whenever there's a program store fetch, or a read cycle, or a write cycle, there's a low on pin 8 of that 'AC08, which, coincidentally is tied to pin 8 of the HC02 (negative logic AND) the output on pin 10 of which generates the E strobe to the LCD. Of course, being a negative logic AND, it requires that there also be a LOW on pin When there's a LOW on either nPSEN or nRD, AND there's a low on the 'HC02's pin 9, which originates from a decoder ('HC138) there'll be a HIGH on pin 6 of the LCD connector, which is its E strobe. Presumably, the decoder has been applied correctly, as this circuit has been in circulation and sold to whoever wanted it, FOREVER, and is known to work just fine. I don't know that I can recommend this circuit, but, since it's slow enough to operate the LCD as a memory-mapped peripheral, you could give it a try. There's no guarantee, BTW, that the LCD channel will work with YOUR LCD, whatever that is, as some require a negative-going contrast voltage on pin 3. If you build one of these, I'd suggest you use a 20K-ohm pot with a 1K-ohm pot at either end, and connect the series comnbination between +5 and V- from the MAX232. That way you can reach whatever contrast voltage is required, yet not risk harming your LCD. Start out with the contrast pot set such that the voltage on pin 3 to the LCD is 0 volts. If you want to build something simple, I can recommend a much simpler circuit. What's more, there's a more convenient monitor than PAULMON that you could use. I'd suggest you spend some time with datasheets and this schematic before proceeding. A calculator might be handy, too. RE |
| Topic | Author | Date |
| I\'m debating this 8052 circuit... | 01/01/70 00:00 | |
| Do you understand why that was done? | 01/01/70 00:00 | |
| I understand, but my debate is not solved. | 01/01/70 00:00 | |
| Avoid the situation! | 01/01/70 00:00 | |
| It should be ... | 01/01/70 00:00 | |
| ... | 01/01/70 00:00 | |
| startup.a51 will do just that unless modified | 01/01/70 00:00 | |
| What's a "startup.a51" | 01/01/70 00:00 | |
| C startup | 01/01/70 00:00 | |
| and if I use my own code... | 01/01/70 00:00 | |
| If you're smart enough to do that ... | 01/01/70 00:00 | |
| MMIO | 01/01/70 00:00 | |
| yes, at osc/12 it's 1 MHz ... but ... | 01/01/70 00:00 | |
| ... | 01/01/70 00:00 | |
| that's crazy | 01/01/70 00:00 | |
| Why worry? | 01/01/70 00:00 | |
| polls? | 01/01/70 00:00 | |
| If you want it to be high-speed, you won't use LCD | 01/01/70 00:00 | |
| experiment with the obvious | 01/01/70 00:00 | |
| Complexity | 01/01/70 00:00 | |
| I think! | 01/01/70 00:00 | |
| If only that were true ... | 01/01/70 00:00 | |
| Think? | 01/01/70 00:00 | |
| ok | 01/01/70 00:00 | |
| Not a matter of guessing.. | 01/01/70 00:00 | |
careful now! | 01/01/70 00:00 | |
| ASM | 01/01/70 00:00 |