| ??? 01/02/08 22:30 Read: times |
#148982 - Begin here Responding to: ???'s previous message |
>>Read the Data sheet.
Okay Reading... >>MSB first or last? MSB first >>8 or 16 bit transfers? 16 bit word >>Data valid when clock is High or low? DIN (data) is sampled on the rising edge of clk--i guess that's High MAX6969 needs CLK, DIN, DOUT, LATCH & OE. I'm slaving this chip--does not need to talk back. >>With BASIC and External memory I do not think you will have a max clock rate issue. Okay thank you. Marl |
| Topic | Author | Date |
| Another bit banged SPI for 8052 | 01/01/70 00:00 | |
| Start | 01/01/70 00:00 | |
| Tried? | 01/01/70 00:00 | |
| schematics? | 01/01/70 00:00 | |
| totally | 01/01/70 00:00 | |
| Antona 8052 board schematics | 01/01/70 00:00 | |
| OK Begin | 01/01/70 00:00 | |
| Begin here | 01/01/70 00:00 | |
| OK | 01/01/70 00:00 | |
| OK II | 01/01/70 00:00 | |
| Basic? | 01/01/70 00:00 | |
| BASIC 52 | 01/01/70 00:00 | |
Excuse my VB6 accent then | 01/01/70 00:00 | |
| "industry standard" SPI | 01/01/70 00:00 | |
| ok '51 "industry standard" SPI | 01/01/70 00:00 | |
| SPI Standardization is a joke... | 01/01/70 00:00 |