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???
01/03/08 05:32
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#148995 - OK
Responding to: ???'s previous message
So you are writing to a 8 bit port.
Let us assume
CLK = 1,LSB
DOUT = 2
LATCH = 4
OE = 8
DIN = ignored

And OE and Latch are active low.(??)
DIN (data) is sampled on the rising edge of clk--i guess that's High

This means it is safe to write data while to clock is high or low

Write to port &HF to init port to 1's

Enable Chip, Write to port &H7
call writeByte(HighByte)
call writeByte(LowByte)
Latch, Write to port &H3  
disable Chip, Write to port &HF

sub writeByte(Byte)
   For X = 0 to 7
      if Byte and &H80 Temp = &H2  'send a 1
      else             Temp = &H0  'send a 0
      Write to port Temp AND &H5   'send bit to port, clk and latch high 
      Byte = Byte * 8              'Shift Byte Left

      Write to port Temp AND &H4   'Clock Low
      'May need a delay here
      Write to port Temp AND &H5   'Clock High (and Data transfers)

   Next X
end sub




This be good for a start check the data sheet to be sure about latch and OE

List of 16 messages in thread
TopicAuthorDate
Another bit banged SPI for 8052            01/01/70 00:00      
   Start            01/01/70 00:00      
      Tried?            01/01/70 00:00      
   schematics?            01/01/70 00:00      
      totally            01/01/70 00:00      
      Antona 8052 board schematics            01/01/70 00:00      
         OK Begin            01/01/70 00:00      
            Begin here            01/01/70 00:00      
               OK            01/01/70 00:00      
                  OK II            01/01/70 00:00      
                     Basic?            01/01/70 00:00      
                        BASIC 52            01/01/70 00:00      
                           Excuse my VB6 accent then            01/01/70 00:00      
   "industry standard" SPI            01/01/70 00:00      
      ok '51 "industry standard" SPI            01/01/70 00:00      
         SPI Standardization is a joke...            01/01/70 00:00      

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