Well, I'm still working on this idea. My datasheet (Atmel AT89S8252) says that the extra pull-up FET is only turned on "during S1P1 and S1P2 of the cycle in which the transition occurs". That would imply that once the '1' is established, the strong pull-up is not reactivated if the pin is pulled low externally.

There is another FET (very weak) responsible for restoring a "lost" '1' but it states that the '1' could be lost by a "negative glitch on the pin" and not just a logic '0', but regardless it is called "very weak" and it doesn't sound like it will have much influence on the use of the pin to sense external logic states (assuming very modest series resistance as we have all agreed.....).