When the CCD linear sensor is exposed to light the numerous pixels are hit by photons. Where the photons hit the depleted area of crystal (like in a photodiode) a proportional amount of charge is formed (concretely spoken separated). This happens during the period where QROG is logic high. The longer QROG is logical high the more photons are collected. It's on you to decide how long QROG is chosen high (usually 1...20 milliseconds): All illuminated pixels must deliver an output signal smaller than the saturation voltage Vsat. This must be checked by a suited piece of code, of course.

When QROG goes low, all the pixels' information (portions of charge) is transferred to an array of capacitors (CCD register) sitting next to the pixels.

Now, the two clock signals Q1 and Q2 are used to transfer each capacitor's charge of the CCD register from one neighbour to the next, all being fed in a row to their according output Vout.

QRS seems to be needed to read out the signal from the capacitor array (CCD register), like shown in figure 14 of this link

http://www.kodak.com/US/en/dig...rPart2.pdf

The first 63 output voltages have nothing to do with the actual pixels, but are helpful to properly interpret the pixels' information. D14 to D62, for instance, allow you to determine the offset voltage Vos, which is superimposed to each output voltage. It provides the "optical black" signal.

And, yes, there's an ADC needed to read the analogue output voltages. Normally, this ADC has to be very fast if the shifting clock rate is high.

Kai