Email: Password: Remember Me | Create Account (Free)

Back to Subject List

Old thread has been locked -- no new posts accepted in this thread
???
03/09/08 06:11
Read: times


 
#152042 - Fast A/D Converter
Responding to: ???'s previous message
The data sheet calls for a typical clock shifting frequency from 1 MHz up to a maximum of 3 MHz. This will correspond to the "pixels" of analog voltages showing up at the outputs at a rate of from 1000 nanoseconds to 333 nanoseconds. Most often an analogue buffer is needed to properly adjust the drive to the converter circuit. Any delay in this buffer circuit will steal from the clock period used and cause the available time for the A/D conversion to be less than otherwise anticipated.

Clocking of this type of device must be watched carefully. I understand that signal integrity of CCD clocks is of utmost concern as undershoot and overshoot of clock waveforms can compromise the image charge storage and thus image quality. Also note that no minimum clock rate has been specified but I have been told in the past that there is always a practical lower limit to the clocking rate below which the image quality suffers due to leakages, thermal noise, and other factors. (Note that I have not verified this first hand but offer it as something to consider).

There are A/D devices you may want to look at that can convert analogue video data rather quickly. Here is one such video decoder that can also function as an RGB digitizer.

http://www.analog.com/en/prod/0...%2C00.html

The fast analogue output requirement out of a scanner CCD device often requires some clever design to deal with the fast data flow rate. In this Sony chip at 1MHz clocking with 3x 5300 pixels to capture at say 8-bits per pixel there will be just under 16K bytes of data to manage for each scan time which is on the order of somewhere between 5 and 6 milliseconds (assuming the 1MHz clock rate the chip specs are referenced to).

For an 8052 design it may be well to use a derivative part that can support a external RAM array. A smallish CPLD or FPGA could be used to create the clocks to run the CCD array, the video decoder/graphics digitizer and digital data DMA process into the RAM. The CPLD could, if enough pins and logic cells are allocated, provide for the dual porting interface into the RAM from the 8052's bus interface.

This sounds like a fun project. It is also certain that you will learn a tremendous amount doing it.

Michael Karas


List of 16 messages in thread
TopicAuthorDate
CCD linear sensor            01/01/70 00:00      
   Link?            01/01/70 00:00      
   CCD            01/01/70 00:00      
   RTFDS            01/01/70 00:00      
   You've got to read the datasheet            01/01/70 00:00      
   Some hints            01/01/70 00:00      
      Thanks Kai,Richard,Andy And Steve            01/01/70 00:00      
      Fast A/D Converter            01/01/70 00:00      
         Thanks Michael,            01/01/70 00:00      
            Further Explanation            01/01/70 00:00      
   More Advice?            01/01/70 00:00      
      I would not consider parallel port.            01/01/70 00:00      
         Windows is probably a poor choice of platforms            01/01/70 00:00      
         Enhanced Parallel port on ISA does 2 MBps            01/01/70 00:00      
      frame grabber            01/01/70 00:00      
   Richard And Michael            01/01/70 00:00      

Back to Subject List