| ??? 03/09/08 16:54 Read: times |
#152045 - Thanks Michael, Responding to: ???'s previous message |
Indeed your answer made me more aware about the subject,
Michael said:
The fast analogue output requirement out of a scanner CCD device often requires some clever design to deal with the fast data flow rate. In this Sony chip at 1MHz clocking with 3x 5300 pixels to capture at say 8-bits per pixel there will be just under 16K bytes of data to manage for each scan time which is on the order of somewhere between 5 and 6 milliseconds (assuming the 1MHz clock rate the chip specs are referenced to). Can you tell me please 5 and 6 milliseconds come from where? For an 8052 design it may be well to use a derivative part that can support a external RAM array. Why RAM is needed while i must send real time data to pc? A smallish CPLD or FPGA could be used to create the clocks to run the CCD array, the video decoder/graphics digitizer and digital data DMA process into the RAM. The CPLD could, if enough pins and logic cells are allocated, Did you meen all ADC Interfacing,CCD Clocking,Sending Data to pc can be done by a Spartan 2 Xilinx FPGA like XC2S150? |
| Topic | Author | Date |
| CCD linear sensor | 01/01/70 00:00 | |
| Link? | 01/01/70 00:00 | |
| CCD | 01/01/70 00:00 | |
| RTFDS | 01/01/70 00:00 | |
| You've got to read the datasheet | 01/01/70 00:00 | |
| Some hints | 01/01/70 00:00 | |
| Thanks Kai,Richard,Andy And Steve | 01/01/70 00:00 | |
| Fast A/D Converter | 01/01/70 00:00 | |
| Thanks Michael, | 01/01/70 00:00 | |
| Further Explanation | 01/01/70 00:00 | |
| More Advice? | 01/01/70 00:00 | |
| I would not consider parallel port. | 01/01/70 00:00 | |
| Windows is probably a poor choice of platforms | 01/01/70 00:00 | |
Enhanced Parallel port on ISA does 2 MBps | 01/01/70 00:00 | |
| frame grabber | 01/01/70 00:00 | |
| Richard And Michael | 01/01/70 00:00 |