A simulator that's properly designed would certainly "know" when the cache is hit and when it is missed, hence, would tell you how many cycles are involved in any segment of code, given the entire context. There's nothing random about cache usage and a simulator will always know whether a given cycle produces a "hit" or a "miss."

The "formula" for power per cycle, is only an estimate, but it's unlikely any manufacturer would claim any better. Nevertheless it will enable you to produce a "best-guess" if you have a cycle count in the context of cache mapping.

I've long been amazed that manufacturers are unwilling to produce a proper simulator for their devices.

I had a KEIL support person once tell me that it was not possible to predict the bus timing of a DS89C4x0. That certainly was incorrect, and it's the reason I've never considered a KEIL product. It's one of the major disconnects between software houses and end-users, as they, the software vendor, seldom have personnel up to the task.

RE