I took dhry.c from the sdcc package, get rid of all printf and timing (I had no intention to get it really working), and compiled with sdcc (an older version but it really does not matter in this case). Dhrystone uses quite a lot of memory so the large model had to be used.

The resulting hexfile was then run through Jeff Post's d52, with the cycle counting on, and the sum of all instruction's duration is presented below (and the files are here). Note that this is not the cycle counts the program would run. As the SiLabs core has a different cycle count for a conditional jump taken/not taken, the two numbers represent the two extrema: all jumps taken/all jumps not taken.

number of instructions      2190
cycle count for "vanilla"   3550 (x12)
cycle count for SiLabs      4534-4610

The cycle/instruction for SiLabs is then slightly above 2, and the "penalty" compared to "vanilla" is around 30%. The cache misses in the 50/100MHz SiLabs are not taken into account (they would be hard to predict in such crude "experiment" anyway).

Discussion: Dhrystone is a syntetic benchmark intended to "excercise" the processor core of "standard" computers. There are quite a lot of arithmetics involved, as well as quite lengthy register push/pop and parameter preparation before function calls. This is not typical for the standard "employment" of '51 - in control applications, where short loops, significant interrupt processing (read: calls/returns) and quite a lot of simple functions call (i.e. without significant parameters passing overhead) occur. I would then still assume the 50% "penalty" as mentioned above as more valid "ratio" for the SiLabs versus "vanilla".

JW