??? 04/14/08 17:35 Read: times |
#153271 - ports structure Responding to: ???'s previous message |
Designers of the original 8051 at Intel tried to make a very useful chip, to be used in a variety of situations with the minimum of surrounding circuitry; and at the same time very cheap (read: with minimum of circuitry inside the chip - today, when transistors inside chips are cheap, ports of modern microcontrollers are configurable into various modes). This is the reason why they chose the quasi-bidirectional arrangement of the ports P1-P3 circuitry - note that it is an order of magnitude more complex than just a simple "pullup resistor" (refer to the "bible" for more details).
Port 0 was intended - among other purposes - also for input of data from external code and data memory. This is why it is a "pure" input, without the pullups, in order not to load the external memories (or a whole bus) extensively. However, note, that in the moments when port 0 emits the low part of address in an external memory cycle, it behaves as a push-pull output. JW |
Topic | Author | Date |
P0 pull up resistors | 01/01/70 00:00 | |
ports structure | 01/01/70 00:00 | |
More Port 0 history | 01/01/70 00:00 | |
Of course, there is a reason for it... | 01/01/70 00:00 | |
Port 0 Pullups WHY??? | 01/01/70 00:00 | |
P0 is multiplexed for input/output; P2 is not | 01/01/70 00:00 | |
This would all be perfectly obvious if only you\'d | 01/01/70 00:00 | |
See this thread | 01/01/70 00:00 | |
Scary Bible | 01/01/70 00:00 | |
Only In Some Cases.... | 01/01/70 00:00 | |
Directly connecting the base will hardly work! | 01/01/70 00:00 | |
Hardly is correct.... | 01/01/70 00:00 | |
what about a darlington? | 01/01/70 00:00 | |
Will also turn off the weak pull-up... | 01/01/70 00:00 | |
The high state is adequate for some things | 01/01/70 00:00 | |
OH![]() | 01/01/70 00:00 |