Interrupt controllers usually manage powerfull features, for example interrupt priority levels.

I think that you can find an inexpensive chip for this application, and this is probably the best option. Even so I shall describe some alternatives.

In the case you only need a simple way to determine what interrupt source has requested service, you can connect the 8 request lines to an 8-bit port and also to a suitable 8-input gate (AND, OR, ... depending on what the active level is, 0 or 1). The gate output is connected to INT0. Your ISR must read the port to determine what interrupt source(s) are active. This approach will not work if the interrupt sources generate requests in the form of very short pulses.
As an alternative, you can use an 8-bit flip-flop with tri-state output control. Each interrupt signal has to be connected to one input, so that the flip-flops memorize the requests. The outputs can be connected to the data bus, so that you can read what source or sources must be serviced. The output enable signal must be driven by an available chip select.
Finally, the SW must clear the requests using for example a dedicated I/O line. Or you can use CS and WR in order to generate the clear signal any time a writting intruction to the flip-flop address is executed.
Some peripherals include the request flip-flop. In this case you can replace the external flip-flop by a tri-state buffer. Then you have to clear the peripherals directly.

Regards,

Alfredo del Rio.