Srinivas,

What you want is done everyday without MX, DS390, i251. This topic has been discussed across many modes of operability and non-operatbility have you searched?

Be careful that you are enabling your RAM. If it is never selected, bus capacitance alone can often "retain" the last driven pin state alowing you to "read" the last data "written".

If you are selecting the RAM and have this problem then look to how you are implementing the hi address.

If you are writing sequentially to multiple pages of RAM you will have to mange DPTR. How do you detect overflow. INC DPTR will not set any PSW flags so it's up to you. A 24 bit addressing routine that copies it result to the latch and DPTR allows carefree access to any location, any page (if your hardware is up and running).

regards,
p