Dear Srinivas,

1. How do you generate Chip select?
Is it grounded permanently? or are you using address decoding logic?

2. What is an individual BANK size in your design?

3. Are you trying to retrieve the data after switching the power from off to on condition ?
I mean , after writing the data into the RAM are you switching off the power?

4. Are you using any ISR in your monitor program?

5. Do you think that there is some problem with logic level Compatibility?
i.e CMOS & LSTTL logic LEVELS.

6. Why can't you introduce wait states after reading or writing data in the SRAM ?.

7. Initialise individual RAM with 0A5H and then try to retrieve the data. Compare it with 0A5H.
If it is O.K then re-initialise the RAM with 5Ah . Again try to retrieve the data and compare it.
By this way u can check individual location in the RAM. This is just for checking the condition
of RAM (GOOD or BAD).

8. I hope you are clear that during the power on state, A18,A17,A16 Of the RAM address lines will be pointed to the
uppermost bank of DS1250 if you are not putting any NOT GATE between AT89C51 and DS1250.
If u r putting a NOT GATE check its logic compatibility.

9. Are u grounding Pin 1 ( /oe) of 74LS 573 AND connecting pin 11 (T input) to Vcc ?.
By the way what is the voltage at Vcc ?.


Regards,

Venkatesh Kamath