Stewart:
The only mention that Atmel makes in their data sheet is in the same place they talk about the ISP procedure to hold PSEN low. If you look there and then down a couple of sentences you will see the comment about removing the low on PSEN 24 clocks after reset is finished.

The test you did and seeing the current at 0.4 mA (400 uA) while reset is on shows that it is important to consider the 24 clock requirement if you are using this ISP entry method.

If I were making this circuit I would drive the PSEN with a small Nchannel MOSFET transistor, i.e. drain to PSEN, source to ground, and gate to an R/C circuit. The other side of the R/C circuit can connect to RESET signal such that the gate drive is a delayed version of the RESET signal. Select the series resistor and gate to ground capacitor such that the delay on the o-scope is somewhat longer than the 24 clock period that Atmel has in the data sheet. I am presuming that the RESET to your Atmel part is the typical 8051 style high true reset. In addition to this you will want to arrange a jumper or switch to disable the RESET to PSEN connection through the circuit when you do not wish the ISP function.

Good Luck
Mike Karas