Richard,

Does any one here have any experience with the Lattice part and/or ispLever s/w ?

Yeah, three designs in the last year, written in Verilog using Leonardo as the synthesis tool.

Relatively straightforward!

I've implemented a design that compiles and can be programmed into the device, but which does not work as expected (it's a simple 8 x d-type ff as a latch with tristate o/p's) it worked before changing to tristate o/p.

I guess the first question is: "What's expected?" I assume that you have some sort of output enable for the pins' tristate drivers. You must obviously make sure there's no contention -- when you're writing to your port, you have to make sure no one else is writing, too!

Dare I ask if you simulated your logic?

-a