Well if you want to use a vhdl buffer with a tristate output then the way I would do it is something like this

entity tris is
port(D_in: in std_logic_vector(7 downto 0);
D_out:out std_logic_vector(7 downto 0);
o_en :in std_logic;
clk:in std_logic);
end tris;
architecture rtl of tris is
begin
process(o_en,clk,D_in)
begin
if o_en='1' then --active low oe
D_out<=(others=>'Z');
elsif falling_edge(clk) then
D_out<=D_in;
endif;
end process;
end rtl;

it uses an implied latch to produce d_type latches because there is no definition for the state where O_EN is low and its not a rising clock which makes VHDL insert latches.