Hello, I am a beginner in 8051 series microcontroller. I saw many reference books and I didn't know how to choose the types of capacitors in order to fit the microcontroller. Why should I use the ceramic capacitors in oscillator circuit in between the crystal? Why should I use the ceramic and electrolytics for power supply to microcontroller? What are the differences between ceramic, metallized film & electrolytics?


Hallo Mack,

first, you must always have a look to datasheet for to see what capacitors are suggested arround quartz of oscillator. Many times 27pF...33pF are recommended. But have a look!
Crystal needs so called burden capacitance to work at his working point. It's defined by manufacturer and it just must be used.
Theoretically, crystal oscillators could be built without additional, to be inserted, burden capacitance. Instead of this, anavoidable stray capacitance and input / output capacitance of gate circuitry, which gives some pF, could be used. But theses capacitances are not stable at all. They highly depend on temperatur and signal voltage. The consequence would be a rather unstable quartz frequency, and advantage of this very precise part would be eliminated. So, 'inventors' of crystal oscillators use a trick: Some additional, very stable capacitance is paralleled to stray capacitance in such a way that additional, very stable capacitance is much bigger than stray capacitance. That's the reason why you shall always add two 30pF capacitors to your oscillator.

Even looking very simple, quartz oscillator is very complex. Making any calculations is difficult. E.g. if capacitors are not equal, then signal voltage can drastically increase or decrease. So, to take full advantage of quartz oscillator burden capacitance must be very stable, of course. This is the reason, why for burden capacitance a certain capacitor type is preferred: NP0 ceramics. This capacitor type has almost neglectable temperatur coefficient and remains stable under temperatur changes. Also long term drift is minimal, means it does not show any relevant aging.
Don't forget to keep connections between capacitors and oscillator pins and ground pins of mcu (microcontroller) as short as possible!!! Every centimeter counts!

Capacitors for power supply decoupling are used for a different purpose. Modern digital chips use a trick for achivieng very fast switching speed:
You know that a classical CMOS inverter circuit consists of two transistors, one (PMOS) switching output to Vcc, the other (NMOS) switching output to ground (0V)? When an output changes logical state from low to high e.g., first, the switched-on NMOS is switched-off, afterwards PMOS, which was switched-off up to now, is switched-on. So, always one transistor is switched-on, while the other is switched-off.
But with this technique fast switching is not possible. So, a trick is used: While NMOS is still switched-on, PMOS does not wait for NMOS totally be switched-off, but is also switched-on. This results in an overlapp condition, where both transistors are partially switched-on. This overlapping lasts some nanoseconds until NMOS is switched-off totally. Of course, during overlapping a big amount of current flows from Vcc pin through switched-on PMOS and switched-on NMOS to ground, something in the range of 50mA for HC-MOS chips. Fortunately, overlapping does not last very long, otherwise both transistors would 'smelt'.

This overlapping has a serious consequence: Current which is internally flowing directly from Vcc pin to ground pin will of course flow not only internally of chip but also through some external wiring. And when such a narrow current spike is flowing through some long and narrow copper traces a desaster is happening: Anavoidable inductivity causes excessive ringing and this results in big voltage drops. The consequence is much high frequency noise on Vcc traces and ground (0V) traces resulting in a big misinterpreting of logical levels at inputs of digital circuitry.

There is only one remedy to prevent this: Not to allow, that spike current flows through whole application. This can be achieved by connecting a capacitor as close as possible to Vcc pin and ground pin. Then, a big amount of spike current is flowing in the following manner: From Vcc pin through turned-on PMOS, through turned-on NMOS and finally to ground pin. This is what internally circuitry forces. This cannot be avoided, it's just funtionality of HC-MOS technology. But now it's becoming interesting: Spike current flows further from ground pin to capacitor connection and THROUGH capacitor back to Vcc pin. It's just what happens when a capacitors discharges, because he shall deliver some current to external circuitry.
As consequence, spike current through external wiring is drastically decreased and voltage drop on Vcc line and ground lines is also drastically decreased, namely from more than 1V down to a few 100mV.

As I told above, decoupling capacitor is discharged by spike current, which is caused by overlapping. Remember, spike lasts about 5nsec and is about 50mA. Data is a rough approximation, of course, but shows correct behaviour in terms of orders of magnitude.
From formula C = dQ / dU and dQ = I x dt we can estimate voltage drop of spike current, when having 100nF for power supply decoupling:

dU = dQ / C = I x dt / C = 2.5mV

That's of course a theoretical calculation, which takes NOT into account voltage drop of spike current accross anavoidable inductivity of capacitor connections. Result only shows, that capacitor is indeed capable to deliver big amount of spike current.

Again connect this capacitor as close as possible to Vcc pin and ground pin, every centimeter counts! Also, use X7R ceramics for 100nF. It's not as stable as NP0, but big capacitances with low volume and low prices can be achieved.

What we calculated so far, is voltage drop of only ONE CMOS inverter stage. But in a mcu there are thousands of such inverter stages, and what is good for only ONE inverter stage becomes poor with THOUSANDS of inverter stages. 100nF capacitor is no longer able to guarantee stable Vcc. So, for decoupling 'bigger' digital chips, decoupling capacitor must be increased. This is normally done by paralleling a bigger capacitor to 100nF. That's the reason, why often an additonal tantal electrolytic or aluminium electrolytic capacitor in the range of 2.2µF...10µF can be seen on PCB.
Unfortunately electrolytic capacitors are not very stable with time and temperature and show poorer high frequency performance than 100nF ceramics. But paralleled 100nF X7R helps them in supporting a good high frequency path for high frequency content of spike current, while big electrolytic prevents Vcc drop.
Tantal are rather expensive but better at high temperatures than aluminium electrolytic. But mostly aluminium electrolytic is sufficient.

Metallized film capacitors are not so widely used in digital applications. May be that price is too high? Just Z5U ceramics, which is not so good as X7R ceramics, is widely used and much cheaper than any other capacitor technology.

Bye,
Kai