Kai:
I have to beg to differ a bit with your explanation. If every CMOS gate structure in a modern IC of only even moderate complexity such as a typical 80C52 microcontroller used 50 millamperes in the manner you describe, spread over 5 nanoseconds the chips would almost instantly blow off their bonding wires as soon as the clocking started up. The designers of CMOS push-pull stages try everything possible in their bag of tricks to absolutely minimize any current flow of this nature, which is called "through current".

Almost all current consumed on a CMOS chip, such as a modern microcontroller, comes from the charging and discharging of the node capacitances which the P & N transistors are expected to charge and discharge. Quite to the contrary of your explanation, the designers make chips faster by making transistors ever smaller and ever lowering the voltage excursions needed to define high and low logic levels on the chip. Why? simple...... I = C*(dV/dT). The current required to run a chip at a particular set of rise/fall times (i.e. the dT term) is proportional the the node capacitances and the voltage excursions required on those nodes. Designers make the transistors smaller and the interconnect narrower to lower the capacitance. They lower the Vcc voltage (along with suitable reductions in the threshold voltages of the P & N transistors) to reduce the node voltage excursions.

This does not take away the need for providing a capacitor right at the power pins of the processor or other ICs on an electronics board. These are needed more than ever now-days. Chips are getting bigger and bigger in terms of numbers of inverters driving capacitive nodes on the chips. One would like to believe that at any given time on a chip there were an equal number of P transistors turning ON as are turning OFF. Likewise it would be hugely beneficial if the number of N transistors turning ON at any given time were matching the number of them turning OFF. If this was the case the average current seen at the Vcc pin or at the GND pin would be averaged out to an almost steady flow. However this balance can never be realistically met in a chip design and so there will be high frequency changes in the demand for current into the Vcc pin and out the GND pin as greater numbers of one type of transistor are turning ON versus OFF. The by-pass capacitors we put on the board act as a stored energy source to supply the high frequency energy requirements for the chip as these imbalanced switching activities happen on the chip. They are required because the distributed inductance and resistance of the power grid and wiring back to the power supply make it very hard for the high frequency current changes needed by the CMOS chip to get there in time.

OK.....couple that with the rest of your explanation and I think that really sums up why capacitors are needed on the board.

Michael Karas