Kai:

OK....I'll take back the words "just plain bogus" and "totally bogus".

I also have to recall the early days of working with HCMOS logic, back around the times of 1980 - 1984 (around the date of the Fairchild publication that you referenced), that it was indeed a bear trying to make quiet boards. Four layer boards with internal PWR/GND planes were way more expensive and not as common in commercial grade development as they are today. The ICs were also all in DIPs; the worst kind for the lead inductance and length of leadframe from pad to pin. It was a bear using the stuff of the time and HC logic was often questioned as a viable alternative if noise was a problem. But then again the needs to do emissions testing on products under FCC edict was just coming into play too.

But today things have changed quite a bit. Design strategies for CMOS logic chips have advanced by multiple orders of magnitude. I think that if one were to measure the Vcc spiking current of unloaded logic gates and high intergration microcontrollers and CPLDs that one would find that it is way way less than the early HCMOS logic chips. A well designed and computer modeled I/O driver cell on a chip of today will have a sneak through current that lasts for a fraction of a nanosecond and will be almost negligible in comparison to the dynamic current needed to drive output node capacitance on a board.

None the less decoupling capacitors, proper power distribution, and suitable power sourcing are more important than ever !!!

Michael Karas