low level logic levels for critical control signals to RAM chips, peripheral chips, on busses etc got its start back in the days when bipolar logic such as TTL was in use. Bipolar logic families, using original 7400 logic as an example, had a low level input noise margin voltage of around 0.4 volts. On the other hand the same logic has a high level input noise margin voltage of something like 1.2 volts and greater. For this reason it was decided that the best inactive level for control signals should be when they were at a high level. This choice was reasoned that you had a better chance then of the avoiding mis-triggering the circuits that used the strobe control signals due to noise spikes. I recall that it was also reasoned the inactive signals would spend a greater percentage of the time in the high level than in the low level so your possibility of random upset due to stray disturbance was also reduced.

My $2.00 worth. (there has been inflation 0.02 is worthless these days).
Michael Karas