I realize I got caught up in discussing this based on discrete logic.
I have not used discrete locic for I/O for ages since I consider it silly not to employ a (C)PLD to lower component count and make easily modifiable logic, after all we all make mistakes and it is a lot easier to reprogram a (C)PLD than to run a new PCB.
Also, calculating all costs - components, insertion, PCB and debug/repair cost - a (C)PLD solution is cheaper.
I do thus need to correct my statement to state what I do today.

Kai wrote:
I try to avoid this situation by additionally gating decoding circuitry with reset signal of supervisory chip. Then, only when Vcc is smaller than about 1V...2V bus contention is possible, but then output impedances are so high that no damaging currents can flow.

I replied:
I have never designed to avoid contention before all port pins are a 1 and never had a problem.

The above statement was correct when I used discrete logic. With (C)PLDs I use reset to set all outputs to open collector.

Erik