All I can say is my drawing was a conceptual block diagram. Detailed design requires analysis that I did not put into the generation of that drawing. As you can see, that drawing was not even able to be considered a schematic.

All that said let me add that it is my experience, based upon some very detailed lab experiments I conducted some years ago on logic gates, that the output pins tend to stay basically 3-stated when the VCC of the logic part is below a certain level. I did these tests by applying a triangle waveform to the VCC pins of the logic parts of various logic families and then putting various types of loads on the gate outputs. These loads consisted of various sized resistors to ground, to VCC, and to VCC/2. The tests also included some loads that were configured as a current source or sink. I had found that the output structures stayed essentially 3-state until the VCC got up to over about 1.2 -> 1.6 volts for 5 volt logic types. This means, from my experience, that the inactive level that is needed on a bus control line during a power up sequence can often be provided via pulling resistor (i.e. to VCC in the case for active low control lines).

However that does not mean that my experience, obtained via direct observation, applies to all logic parts and/or any particular type of microcontroller. It also means that if you use additional external logic to qualify and/or disqualify bus control lines with the RESET signal you MAY or MAY NOT obtain the real result you intended. The logic gate doing the qualification may itself have a 3-state condition on its output! In addition to that the device with which you hope to keep disabled may not even need disabling because its outputs could be similarly in a 3-state condition at the lower VCC levels.

So it is tough to try to generalize and say that any given design needs to be taken to the extent of declaring - "Oh I put logic that disables the control lines at reset in every board I do." Instead it is well to study the boards you make and see how the busses and control lines work, using a good oscilloscope and a controlled power supply source with a repeatitive drive to it. Often I have used a big old NPN power transistor running in emitter follower mode into a small valued resistor in parallel with the VCC connection to the board under test. The base of the power transistor being driven with a triangle wave from a function generator at about 100 Hz or so.

This kind of analysis can take a lot of time but it is really the only way to come to understand how the parts in a design will interplay during a power-up and a power-down sequence. And this information is rarely included in a data sheet!!! These factors are part of the reason that I seek out a somewhat standard configuration of hardware that I evaluate and make sure works correctly and then keep applying the same structure to various projects if possible. It is also the reason I prefer to do designs with just one chip on a board such as a Cygnal part. I can pick a part with anywhere from 10 to 64 or more I/O lines and rarely find a need to build bus structures on a board of an embedded product.

And to you Abhishek: Promoting a concept to suggest the use of an 8085 + 8755 on a design ??? What decade are you living in man ??? It is 2003 not 1986. I would not recommend any such concept and it's almost as bad as suggesting that somebody should use an original NMOS 8048 or 8051 in a design as opposed to the far more effective derivative parts of today with all the on-board facilities that you need plus ISP, IAP, and in some cases ODH (on-board debug hardware). I bet you don't cruise the web or participate in this forum using a 8085 based computer running CP/M at 3.579 mHz. Heck maybe you should....you could code up your own web browser and windowing environment, and when you run out of program space at 56K you could support a swap space on a 8" FDD.

Michael Karas