Hello Erik,

I am just reproducing a portion from the PLD QuickStart Handbook by Xilinix ( Free download PDF ):

" Another inherent problem with using schematic capture is the
difficulty in migrating between vendors and technologies. If you
initially create your 10,000 gate design with FPGA vendor X and then
want to migrate to a gate array, you would have to modify every one
of those 50 pages using the gate array vendor’s component library!
There has to be a better way...
And of course, there is. It’s called High Level Design (HLD),
Behavioural or Hardware Description Language (HDL). For our
purposes, these three terms are essentially the same thing."

Now I am a bit confused. I am sure I am not getting the whole picture and without any hands on experience cannot share "my" views. Could you clarify a little bit more on this ?

Thanks

Raghu