Another inherent problem with using schematic capture is the difficulty in migrating between vendors and technologies. If you initially create your 10,000 gate design with FPGA vendor X and then want to migrate to a gate array, you would have to modify every one of those 50 pages using the gate array vendor’s component library!
There has to be a better way...
I do not use schematic capture, but I know some that state that they can not do it any other way. As faqr as I'm concerned, the 'boolean logic entry' is the way to go.

And of course, there is. It’s called High Level Design (HLD), Behavioural or Hardware Description Language (HDL). For our purposes, these three terms are essentially the same thing."
For boolean entry there are two older 'languages', ABEL and CUPL, both those can be compared to assembler. There is then Verilog and VHDL which both are trying their best to "abstract" you from the hardware. They are both, in my opinion, very cumbersome to use. So I hum happily along using ABEL which is supported by the Lattice software and others.
Now I am a bit confused. I am sure I am not getting the whole picture and without any hands on experience cannot share "my" views. Could you clarify a little bit more on this ?
Hope the above do

Erik