Another way to deal with the issues Michael addresses, but without disabling interrupts, is to have the ISR set a set a "TIME_IS_DIRTY" bit whenever it changes one of the HH:MM:SS "registers" ("dirty" borrowed from cache terminology). Then when the non-ISR code goes to read the multiple bytes, it first clears the "dirty" bit, then reads HH:MM:SS, then checks to see if its read was "dirtied" by the ISR during read and if so, loop back around to clear the "dirty" bit and try again.