The HT9032 chip is unbuffered and as such the microcontroller must be ready to take the data immediately when it becomes available. It appears to me that the DOUTC/ (not the DOUT/ pin) pin of the decoder chip could be connected to the RxD pin of a microcontroller UART to perform the serial to parallel conversion and receiving function. So one solution that seems the easiest is to provide one UART for each of the 32 decoder chips. This can done with low cost 8051s to collect the data and them provide it to the main controller via some other type of interface such as I2C.

Alternatively you could code up a software state machine that was able to scan each line at 16x the CLI data rate and demodulate the serial bit stream in software. There are some ideas on this concept at the Silicon Labs (formerly Cygnal) web site in App Note #115. (at this link: http://www.silabs.com/products/pdf/an115rev1_1.pdf ).

This state machine could work if you made an interrupt that ran at 16X the 1200 baud data rate it would be an interrupt at 19200 Hz. This corresponds to a time of 52.08 microseconds. Then if you used a high performance type of microcontroller such as a Cygnal type running at 25 MHz with its 1X bus cycle (40 nsec per) divide rate you can achieve a processor performance of 52.08/.040 = 1302 bus cycles per interrupt time. If you left about one half of the available bus cycles to the application program and system interrupt overhead you could anticipate an availability of some 640 bus cycles available for running the 16X data rate state machines. These cycles would need to be divided evenly between the number of software UARTs that you were trying to implement on this one processor. If you tried 32 UARTS that leaves about 20 bus cycles (640/32) per UART per sample period. To me this is not a practical solution. I think if you worked in assembly language and coded carefully it would be possible to build the UART sample time decoder in for each state machine state in about 40 bus cycles (On a Cygnal 1X part that would average about 25 instructions).

I would conclude that a Cygnal type 1X processor such as a C8051F226 part running at at 25 MHz could software decode 16 DOUTC/ pins from Holtek '9032 chips. Your job would require 2 chips.

Now if you elect to use an alternate type of processor with a different frequency or bus cycle divider then these calculations need to scale accordingly. For example the much discussed Philips 89LPC932 operates with a 2X cycle divider and can use a crystal of 12 MHz. This part has bus cycles of 166 nSec which is roughly one quarter the performance of the above mentioned Cygnal part. This would lead to an estimate that one 'LPC932 could decode 4 lines and that you would need 8 of these chips to decode the outputs from 32 Holtek chips.

On the other hand Cygnal has parts that can clock at 50 MHz with a 1X bus cycle divider. At this setup this would offer twice the performance over the above recommended '226 chip and you could anticipate doing the decoding for all 32 Holtek decoders using a single microcontroller provided you had enough I/O pins available.

The number of I/O pins is another consideration too. I think you need a minimum of 2 pins per channel (DOUTC/ and the RING_DET). A pair of Cygnal C8051F020 chips @ 25 MHz and 64 I/O per part seem like a quite adequate solution to your job.

Michael Karas