Nah i like the idea of a simple multiplexor,possibly with some syncronisation signal,a very basic mutiplexor which will select 8 bit slices from a 32 bit input could be used as the basic starting point.I ca be done like this in vhdl for a cpld.

library IEEE;

use IEEE.std_logic_1164.all;

entity mux is

port( cli_in : in std_logic_vector(31 downto 0);
sel : in std_logic_vector(1 downto 0);
slice_out: out std_logic_vector(7 downto 0));


end mux;


architecture rtl of mux is
begin
with sel select
slice_out<=cli_in(31 downto 24) when "00",
cli_in(23 downto 16) when "01",
cli_in(15 downto 8) when "10",
cli_in(7 downto 0) when "11",
'X' when others;
end rtl;