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???
05/24/04 09:57
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#71034 - RE: AD7718 and P89C51RB2
Responding to: ???'s previous message
hi,

Sorry, what does confuse you? When you do software reset then part comes to default state then waits for a write operation to the Communications Register.
The additional read cycle of 24 serial clocks is required because DIN and DOUT are connected together; so if AD7718 was in state where it transmits data, we need to flush all these data out (up to 3 sequental bytes) before start to transmit 32 clocks of DIN high. Otherwise some data come out from DOUT may conflict with ones we send to DIN. So at first step we read 24 bits from device (which are not defined and may be at low/high state) and only after it we perform write 32 high bits of '1's.

Regards,
Oleg

List of 8 messages in thread
TopicAuthorDate
AD7718 and P89C51RB2            01/01/70 00:00      
   RE: AD7718 and P89C51RB2            01/01/70 00:00      
      RE: AD7718 and P89C51RB2            01/01/70 00:00      
   RE: AD7718 and P89C51RB2            01/01/70 00:00      
      RE: AD7718 and P89C51RB2            01/01/70 00:00      
         RE: AD7718 and P89C51RB2            01/01/70 00:00      
            RE: AD7718 and P89C51RB2            01/01/70 00:00      
   Problem solved! Thanks.            01/01/70 00:00      

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