Dear Raghu:
Hello, To the best of my knowledge a memory a flip bit can happen due to one of the following scenarios:
1-software bug: In the case that the program is really complex it may happen that the bit be changed by an unseen bug.
WAITLUP: CLR FLG_SYSOK
CALL MSG_NOTOK
JNB DIN_SYSOK, EXITSCAN
SETB FLG_SYSOK
...
...<- bit status may be changed due to an unseen bug.

WAIT4START: JNB FLG_SYSOK, EXITSCAN
CALL MSG_STRPB
JNB FLG_START, EXITSCAN

Suggestions : if it is possible check the status of DIN_SYSOK just before WAIT4START. If it is not possible program may write the value of DIN_SYSOK in two or three different locations of ram (for example in data, idata and xdata) then and(&) them before diverting the program to STARTSEQ and if the anded value and the ored value differed software may report a failure and/or reset MCU.

2-EMI: In the case that PLC output connected through some glues to MCU, the output should have reasonably low impedance to be immune from EMI.
3-Power supply spikes : Power supply should be solid rock stable. Spikes in power supply can lead to flipped bits.
4-Are sufficient number of parameters are checked to produce a SYSOK signal ?
In some of my designs that needed extra reliability I have used back up external hardwares to double check validity of the system.

Best Regards
Reza Fallahati