hi,

Since the port on the micro is made high when using it as an input port, I think I will not need a level translator in this case. Is this a reliable setup?

The problem is that MISO of MCU is in P1. Although it is input function of pin, nevertheless the pin has internal pull-up connected. And this pull-up is connected to 5V. What we have as result? CMOS output of 3V device is connected to the 5V with pull-up.

Well, now there is some theory. Do you know what is the "latchup" effect? The CMOS output has parasite pnpn silicon-controlled rectifier (SCR)-type structure.
And so here we have: when output voltage is more than ~3.7V then parasite pnp transistor will be opened with current of the 5V pull-up and then the whole structure is latch-upped. As result, 3V will be shorted to ground will high current. This current is enough to destroy whole CMOS output/chip.

Fortunatelly, most CMOS devices has been protected from it with clamp Schottky diodes built-in. Twice fortunatelly that pull-up of MCU cannot source high current (max. about 100..150μA) and so clamp diode is not overloaded.

This example may show you that it is not so simple just mix 3V and 5V devices.

Regards,
Oleg