If you are asking if you can implement the Vernier timing technique using a normal cpld then the answer is not very easily,if you wish to use the technique as outlined in the app note then you need to use either a delay locked loop as found in xilinx spartan and virtex fpga's or a phase locked loop as found in altera and other fpga's because generating the clocks with the correct relationships is a little tricky.
I hadnt actualy dissapeared entirely,just an ickle bit.