From the user guide:
"The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows"

you write:
creating an interrupt if the SFR underflows.
but it also create a reset

The problem I have is with the feeding sequence. 2.5 seconds after I initialize it, it creates an interrupt, I implement the feed sequence
a watchdooge should be fed before it underflows or a reset will occur.

Also, to verify this I notice that when the ISR is executed those registers (WFEED1 & WFEED2) are still 0x00.
1) they are probably write only
2) the interrupt occur when the counter underflows (=0)

Erik