It can be made into a very usefull 51 compatable controller and with a bit of tweaking it should run at 25-30 Mhz in a bog standard FPGA which at 1 instruction per clock cycle makes it equivelent to a standard 8051 running at about 300-360 Mhz.Of couse the 3 stage pipeline means that branches and interupts cause the pipeline to stall.
Its been abandoned because when it was written things like the single clock multiplier/divider and the internal Ram would have made it too big I think.Modern FPGAs have multipliers and dual port RAMs built in.