I understand the fun part of it - many years ago I was involved in the building of a 32bit processor out of bit slice clocked at 27mhz with a 128bit writable control store made of of lots of high speed 1k*4 rams. I learnt the fundamentals of building cpus. Recently I had to build a 16 channel, 16 bit compare unit so I used a fpga. The fun for me was seeing how I could make it the most efficient in gate count and performance. I did it in schematic capture and optimised the floorplan manually.

The concept of 'hard core' cpus on the die with a field of gates makes good sense to me. The silicon area of a powerpc is probably less than that of a 8051 implemented as a soft core - and probably draws less power! Today a 50kgate device is fairly cheap but you'd have to think hard as to whether it would be economical to use 1/5 of it for a cpu. Then you have the peripherals - uarts can suck up to around 2-3k gates each depending on the features.

Obviously, the way the technology is progressing this argument will have less weight - I suppose it's a bit like 'c' on a 8051 - years ago you would not even consider it, nowadays its the norm - we've got lots more performance, ram and code space.