| ??? 12/01/04 15:44 Read: times |
#82301 - " Responding to: ???'s previous message |
"Actually, an interrupt is generated only if the ES bit is set in the Interrupt Enable (IE) register"
Sould be: ES and EA bits are set |
| Topic | Author | Date |
| THE TIME OF TI | 01/01/70 00:00 | |
| Bitrate | 01/01/70 00:00 | |
| interrupt-driven | 01/01/70 00:00 | |
| Why interrupt driven? | 01/01/70 00:00 | |
| UART Serial Port Interrupt | 01/01/70 00:00 | |
| all the above | 01/01/70 00:00 | |
| UART communication by UART interrupt | 01/01/70 00:00 | |
| just TI=1 | 01/01/70 00:00 | |
| serial interrupt in adc interrupt | 01/01/70 00:00 | |
| start with something simple | 01/01/70 00:00 | |
| misunderstand behaviour | 01/01/70 00:00 | |
| See the examples | 01/01/70 00:00 | |
| not has to, but can | 01/01/70 00:00 | |
| The difference is | 01/01/70 00:00 | |
| " | 01/01/70 00:00 | |
| He's right | 01/01/70 00:00 | |
| How the 8051 UART works | 01/01/70 00:00 | |
| The TI-bit Set Time | 01/01/70 00:00 | |
| no, at the middle | 01/01/70 00:00 | |
| The Transmitter Part, Actually | 01/01/70 00:00 | |
| Setting of TI | 01/01/70 00:00 | |
| sometimes chip designers listen | 01/01/70 00:00 | |
| So, Erik | 01/01/70 00:00 | |
| where does it happen | 01/01/70 00:00 | |
| Mode 1 TI timing. | 01/01/70 00:00 | |
| How to post code | 01/01/70 00:00 | |
RS485 & bus turnaround | 01/01/70 00:00 |