| ??? 12/01/04 17:23 Read: times |
#82308 - no, at the middle Responding to: ???'s previous message |
I think that TI-bit is set at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes (see for instance figure 14 on the page 13 of the 51-bible).
The detection of bits is done in the middle of the slot (at, as I remember at 7,8 and 9 counts of the 16*bitrate counter). Thus the bit decision is take at the middle of the bit. So reworking your statement "at the beginning of detection of the stop bit in the other modes" Thus it will appear in the middle of the stop bit as far as the data line is concerned. By the way, what is the minimal time between two transmitted bytes? zero Erik |
| Topic | Author | Date |
| THE TIME OF TI | 01/01/70 00:00 | |
| Bitrate | 01/01/70 00:00 | |
| interrupt-driven | 01/01/70 00:00 | |
| Why interrupt driven? | 01/01/70 00:00 | |
| UART Serial Port Interrupt | 01/01/70 00:00 | |
| all the above | 01/01/70 00:00 | |
| UART communication by UART interrupt | 01/01/70 00:00 | |
| just TI=1 | 01/01/70 00:00 | |
| serial interrupt in adc interrupt | 01/01/70 00:00 | |
| start with something simple | 01/01/70 00:00 | |
| misunderstand behaviour | 01/01/70 00:00 | |
| See the examples | 01/01/70 00:00 | |
| not has to, but can | 01/01/70 00:00 | |
| The difference is | 01/01/70 00:00 | |
| " | 01/01/70 00:00 | |
| He's right | 01/01/70 00:00 | |
| How the 8051 UART works | 01/01/70 00:00 | |
| The TI-bit Set Time | 01/01/70 00:00 | |
| no, at the middle | 01/01/70 00:00 | |
| The Transmitter Part, Actually | 01/01/70 00:00 | |
| Setting of TI | 01/01/70 00:00 | |
| sometimes chip designers listen | 01/01/70 00:00 | |
| So, Erik | 01/01/70 00:00 | |
| where does it happen | 01/01/70 00:00 | |
| Mode 1 TI timing. | 01/01/70 00:00 | |
| How to post code | 01/01/70 00:00 | |
RS485 & bus turnaround | 01/01/70 00:00 |